Multiplier having an optimum arrangement of anding circuits and adding circuits

ABSTRACT

A multiplier in which m-1 place multiplicands can be operated with the multiplier with n-1 place multiplier factors that are represented as binary numbers. In order to achieve a regularly constructed and easily testable arrangement of the multiplier on a chip, one cell (SL) is provided per product place. This cell is composed of AND circuits (UD) for the formation of the partial products allocated to this product place and of adder circuits (AD) for summing up the partial products for this product place. The number of AND circuits and of adder circuits is identical for all cells (SL). Those AND circuits that are not required per product place for generating partial products are applied to 0. Since the individual cells are identically constructed, they can be easily produced from basic circuits and can be easily arranged side-by-side. When a multiplier for multiplicands and multiplier factors having greater width is then to be produced, a further attachment of such cells is merely required.

BACKGROUND OF THE INVENTION

The multiplication of x-place multiplicands (x=0, 1, 2. . .m-1) by ay-place multiplier factor (y=0, 1, 2. . .n-1) (m and n are whole,positive numbers) that are represented as binary numbers can beimplemented according to FIG. 1. This shows a matrix MA that containsthe partial products PP that arise in the multiplication. Themultiplicand is thereby referenced A and the multiplier factor isreferenced B. The partial products can be generated from the multiplierfactor place and the multiplicand place with AND circuits. A productplace P is generated by summing up the partial products per column ofthe matrix. A carry from the next, less significant place of the productis thereby also to be taken into consideration. Three fields can bedistinguished in FIG. 1. Field III recites the partial products that arenecessary for the multiplication. Field I recites partial products thatare not necessary in the multiplication; the same is also true of FieldII. The places of the matrix are recited with 0 in these Fields I andII.

AND circuits that form the partial products and adder circuits that sumup the partial products per column are thus required in order toconstruct a multiplier that multiplies according to the matrix ofFIG. 1. When such a multiplier is to be realized, it is necessary thatthe AND circuits and the adder circuits are arranged in an especiallyadvantageous way in order to create a realization on one chip withoptimally low space requirement and optimally favorable transit timeconditions. It is also necessary that such a multiplier can be veryeasily tested.

SUMMARY OF THE INVENTION

The object underlying the invention is comprised in specifying amultiplier that is constructed such that it satisfies the above-reciteddemands. In addition, the structure should be such that a multiplierhaving variable multiplicand word width and multiplier factor word widthcan be easily manufactured.

For achieving this object, the multiplier for operating a m-placemultiplicand and an n-place multiplier factor both of which arerepresented as binary numbers comprises

a) m+n cells arranged side-by-side, respectively one per product place,whereof each cell respectively contains AND circuits for forming thepartial products allocated to the product place and adder circuits forsumming up the partial products for this product place,

b) the following relationship of the AND circuits and adder circuitswithin a cell:

each AND circuit is composed of at least two AND elements, whereof eachoperates one bit of the multiplicand and one bit of the multiplierfactor to form a partial product,

an adder circuit of the first stage operates the respective partialproducts generated by an AND circuit to form a partial sum and a partialcarry,

adder circuits of the second stage operate respectively at least twopartial sums of the first stage of the same product place and at leasttwo partial carries of the first stage of the next-less significantproduct place to form a further partial sum and a further partial carry,

adder circuits of the third stage operate respectively at least twopartial sums of the second stage of the same product place and at leasttwo partial carries of the second stage of the next-less significantproduct place to form a further partial sum and a further partial carry,

the operation procedure is repeated with the assistance of the addercircuits utilized tree-like in the individual stages until the pluralityof partial sums and of partial carries from the next-less significantproduct place generated in a stage of the same product place is suchthat it can be operated with a final adder circuit to form a final sumbit and a final carry bit,

the final sum bit of a product place and the final carry bit of thepreceding product place are operated in an adder circuit to form a valueP of the corresponding product place, and

c) the following arrangement of the AND circuits and adder circuitswithin a cell:

a first AND circuit is followed by an adder circuit of the first stage,

this adder circuit of the first stage is followed by a second ANDcircuit to which an adder circuit of the first stage for the outputsignals of this AND circuit adjoins,

the adder circuit of the first stage is followed by an adder circuit ofthe second stage for the preceding adder circuits of the first stage,

this sequence is repeated until two adder circuits of the second stagehave appeared, the last adder circuit of the second stage is thenfollowed by an adder circuit of the third stage that operates the outputsignals of the adder circuits of the second stage,

this succession is continued in accord with the preceding steps untilthe final adder circuit has appeared.

It is especially beneficial for the realization on a semiconductormodule and for the testability of the module when the multiplier isregularly constructed. All cells of the multiplier should thereforecomprise an identical plurality of AND circuits and an identicalplurality of adder circuits. What this means is that an AND circuit isalso provided for the partial products lying in Field I and Field II,this AND circuit then generating the partial product 0. To that end, themultiplicand input of the AND circuits can be set to 0. This is validfor that case wherein the multiplicand and the multiplier factor arewithout operational sign.

When, by contrast, binary numbers having operational sign are to bemultiplied, then it is advantageous to select the two's complementrepresentation of these binary numbers. In this case, one input of theAND circuits that generate the partial products lying in Field II areconnected to the most significant bit (MSB) of the multiplicand thatcontains the operational sign. These multiplicand places are alsosupplied inverted to the AND circuits that operate the most significantbit of the multiplier factor with multiplicand places. Finally, the mostsignificant bit of the multiplier factor must also be added in then-1^(th) product place.

The arrangement of the AND circuits and of the adder circuits in a cellis expediently selected such that the connecting lines are optimallyshort. It is thereby expedient that every AND circuit is composed offour AND elements, whereof each operates one multiplicand bit with onemultiplier factor bit. Such an AND circuit is followed in the cell by anadder circuit of the first stage. This is followed by a second ANDcircuit that is in turn followed by an adder circuit of the first stage.The adder circuits of the first stage operate the partial products ofthe AND circuits. The adder circuit of the first stage is then followedby an adder circuit of the second stage that sums up the results of thetwo, preceding adder stages of the first stage. The further units of thecell follow on another in a corresponding arrangement, i.e. a furtheradder circuit of the next-higher stage is utilized when the results oftwo adder circuits of less-significant stages are to be summed up.

It is advantageous for the test mode that the plurality of multiplicandbits is doubled and the partial products (Field II) that therebyadditional arise are formed from the MSB of the multiplicand and of themultiplier factor bits; that, further, the plurality of multiplierfactor bits is always expanded by a number divisible by four, wherebythe most significant bit of the expansion in the operating case 0 isvariable in the test case, the less significant bits of the expansion inthe operating case equal to the MSB of the multiplier factor areindividually adjustable in the test case. It becomes possible in thisway to individually test all AND circuits.

Further developments of the present invention are as follows.

Given an uneven plurality of adder circuits within a stage, an addercircuit of this stage and an adder circuit of another stage areconnected to the adder inputs of an adder circuit of a higher stage.Every adder circuit is composed of two full adders following one anothereach of which has respectively three inputs. Also, every AND circuit iscomposed of four AND elements whereof each operates on one multiplicandbit and one multiplier factor bit.

An adder circuit is connected in the following way: three partialproducts are received at the three inputs of the first full adder; thefourth partial product is received at an input of the second full adder,the sum bit of the first full adder is received at the second input, acarry bit from the first full adder of the adder circuit of the firststage allocated to the next-less significant product place is receivedat the third input. An adder circuit of a more significant stage isconnected in the following way: the sum bit from an adder circuit of aless significant stage is received at the first input of the first fulladder, a respective carry bit from the carry output of the addercircuits of the lower stage allocated to the next-less significantproduct place is received at the second and third inputs; the sum bit ofan adder circuit of the less-significant stage is received at the firstinput of the second full adder, the sum bit from the first full adder ofthe same stage is received at the second input and a carry bit from thefirst full adder of the adder circuit of the same stage allocated to thenext-less significant product place is received at the third input.

All cells have an identical plurality of AND circuits and an identicalplurality of adder circuits. The multiplicand input of AND circuits thatgenerate partial products (Field I) that are not required for generatingthe value of the less significant product places is set to 0. Themultiplicand input of AND circuits that generate partial products (FieldII) that are not required for generating the value of the moresignificant product places is set to 0 given multiplication of numberswithout an operational sign.

For multiplication of binary numbers in two's complement representation,the multiplicand input of AND circuits that generate partial products(Field I) not required for generating the value of the less significantproduct places is set to zero. The multiplicand input of AND circuitsthat generate partial products (Field II) that are not required forgenerating the value of the more significant product places is connectedto the most significant bit of the multiplicand. The multiplicand bitsto be operated on with the operational sign bit of the multiplier factorare connected to the allocated AND circuits. The most significant bit ofthe multiplier factor is then added at the products place where at themost significant bit of the multiplier factor is operated on with theleast significant bit (A₀) of the multiplicand.

For test purposes and given a multiplication of binary numbers of two'scomplement representation, the plurality of multiplicand bits isdoubled. The additional partial products (Field II) formed as a resultthereof are formed of the most significant bit of the multiplicand andof the multiplier factor bits. The plurality of multiplier factor bitsis always expanded to a number divisible by four, whereby the mostsignificant bit of the expansion is zero in the operating case and isvariable in the test case, the less significant bits of the expansion inthe operating case equal to the most significant bit (B_(n-1)) beingindividually adjustable in the test case. The AND elements of ANDcircuits that generate partial products in the Field I are connected tothe least significant bit (A₀) of the multiplicand in the test case.Also, those AND elements of AND circuits that form partial products withinverted multiplicand are supplied with these multiplicands non-invertedin the test case.

An AND circuit having the following AND elements is contained in thelast row of AND circuits: one AND element via which the allocatedmultiplicand bit is supplied inverted in the operating case but to whichthis multiplicand bit is supplied non-inverted in the test case; one ANDelement to which the most significant bit (B₁) of the multiplier factorexpansion is conducted and at whose output a multiplier is arranged thatthrough-connects either the output signal of the AND element in the testcase or, in the operating case, the most significant bit (B_(n-1)) ofthe multiplier factor further AND elements that form either partialproducts of the allocated multiplicand bits or multiplier factor bits orthe expansion thereof. In the test case, the carry inputs of the addercircuits all coated to the least significant product place (P₀) areconnected to one another in the following way: the carry input of thesecond full adder of an adder circuit of the first stage is connected tothe carry output of the first full adder of this stage; and the carryinputs of the first full adder of the second stage are connected to thecarry outputs of the second full adder of the adder circuits of thefirst sage, etc., so that the carries successively run through theindividual adder circuits of successive stages.

The multiplier of the invention is distinguished by high processingspeed that is only logarithmically dependent on the multiplier factorword width. It can be completely tested with a low number of testpatterns. The multiplier is realizable in the multiplier factor wordwidth, for example in steps of 4 bits, in steps of 1 bit in themultiplicand word width. The layout is extremely regular and can beproduced by a program. The multiplier can multiply both positive binarynumbers as well as binary numbers in two's complement representation.The regular structure of the multiplier of identically constructed cellsper product place also facilitates the production of multipliers thatoperate multiplicands and multiplier factors having different wordwidth.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention shall be set forth in greater detail with reference toexemplary embodiments that are shown in the figures. Shown are:

FIG. 1 a partial product matrix;

FIG. 2 a corresponding matrix for the multiplication in two'scomplement;

FIG. 3 a matrix for the multiplication in two's complement whereinmultiplier factor and multiplicand have been expanded for test purposes;

FIG. 4 a circuit diagram that shows the interconnection of AND circuitsand adder circuits per product place,

FIG. 5 a schematic illustration of the arrangement of the cells giventhe multiplication of positive numbers;

FIG. 6 the arrangement of the cells given the multiplication in two'scomplement representation;

FIG. 7 the succession of AND circuits and adder circuits within thecells;

FIG. 8 through FIG. 12 AND circuits that are employed for operating thepartial products;

FIG. 13 the execution of an employed multiplexer;

FIG. 14 the execution of an xnor circuit;

FIG. 15 the execution of the adder circuit;

FIG. 16 a schematic illustration from which how the multiplicand bitsare supplied to the multiplier follows;

FIG. 17 a schematic illustration from which how the multiplier factorbits for the AND circuits in Field I are supplied follows;

FIG. 18 a schematic illustration regarding the supply of the multiplierfactor bits;

FIG. 19 a circuit diagram from which how the carry inputs of the addercircuits of the least significant cell are connected in the test casefollows.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 shows a matrix of partial products that arise given themultiplication of positive numbers. The partial products required forforming the product are thereby arranged in Field III For reasons ofregularity, the Field I and the Field II are additionally shown, thepartial products being respectively 0 therein. These regions are notrequired for forming the values of the product places P. A m-placemultiplicand A is multiplied in FIG. 1 by an n-place multiplier factorB.

When a multiplication is to be implemented with binary numbers thatcontain operational signs, then it is expedient to employ two'scomplement representation therefor. FIG. 2 shows a matrix correspondingto FIG. 1. This recites the multiplication of the multiplicand A₀through A₃ by the multiplier factor B₀ through B₃. The Field III inwhich the partial products that are necessary for the multiplication arerecited is shown first. It is thereby striking that the multiplicandbits are employed inverted in the penultimate row of the matrix whereinthe most significant bit B₃ of the multiplier factor that represents theoperational sign is operated with the corresponding multiplicand bits.Due to the two's complement representation, the most significant bit B₃must also be additionally added in the product place P₃ in which theoperation result of the least significant bit (LSB) of the multiplicandA₀ with the most significant bit (MSB) B₃ of the multiplier factorensues. Field I in FIG. 2 corresponds to that in FIG. 1. It is thusfilled with zeros, whereas the Field II in FIG. 2 is treated differentlythan in FIG. 1. Partial products wherein the most significant bit A₃ ofthe multiplicand is respectively operated with allocated places of themultiplier factor B₀ through B₂ reside here. The product places P₀through P₆ then arise at the lower edge of the matrix. A further productplace P₇ for a potential carry can also be provided.

For reasons of regularity, it is meaningful that the partial productslying in Field I and Field II are also generated. Partial productsrespectively allocated to the individual product places P are thenobtained, these lying in the columns of FIG. 2. An identical number ofpartial products is present in every column; correspondingly, anidentical number of circuits for generating the partial product percolumn must be provided.

The multiplicand A has already been expanded in FIG. 2, namely by threeplaces. The most significant bit A₃ of the multiplicand is respectivelyutilized for the multiplicand places A₄, A₅, A₆. A correspondingexpansion of the multiplier factor is meaningful for test purposes. FIG.3 shows a matrix for such a case. The expansion of the multiplier factorensues such that the size of the expanded multiplier factor B isdivisible by 4. Four places would then have to be added in a matrixcorresponding to FIG. 2. The expanded multiplier factor bits B₄, B₅, B₆are thereby set equal to the most significant bit B₃ of the multiplierfactor; in the operating case, by contrast, the expanded multiplierfactor bit B₇ is set to 0. This expansion has no influence in theoperating case since the multiplier factor is correctly represented intwo's complement. In the test mode that shall be set forth later,however, each expanded multiplier factor bit B₄ through B₇ can beindividually driven and an individual check of the individual circuitsemployed for the formation of the partial products can thus beimplemented.

How the multiplier is constructed shall be set forth below. This therebyproceeds on the basis of the matrix of FIG. 3 as a rule.

FIG. 4 yields the principle of a circuit with which the value iscalculated for a product place P. This means that a circuit of FIG. 4 isallocated to a column of the matrix. In the example of FIG. 4, amultiplicand and a multiplier factor having a word width of 16 bits areoperated with one another. The generation of the partial products ensueswith the assistance of AND circuits UD, whereby each AND circuit UDcontains four AND elements whereof each AND element forms a respectivepartial product. In accord therewith, each AND circuit UD outputs fourpartial products at the output, these being respectively summed up in anadder circuit. The adder circuit AD must thus be constructed such thatit can sum up four bits. A corresponding circuit derives from FIG. 15.This means that the adder circuit AD turns four input signals into twooutput signals, a sum bit SB and a carry bit CB.

Every AND circuit UD thus has an adder circuit allocated to it thatshall be referred to as adder circuits of Stage 1. These adder circuitsare referenced ADI. When a plurality of adder circuits ADI are present,their output values, the sum bit SB, must be summed-up further. Thisensues with the assistance of adder circuits of Stage 2 that arereferenced ADII. In FIG. 4, yet a further adder circuit, namely one ofStage 3, is required, this being referenced ADIII and the values S (sumbit) and C (carry bit) for the product place being then output at itsoutput. The adder circuits AD are all identically constructed, i.e. theyoperate four input signals to form two output signals, a sum bit and acarry bit. The carries CB that are generated by the adder circuits ADIand ADID of this product place proceed to adder circuits of thenext-higher product place. The carries that are required for theaddition of this place are supplied by the adder circuits of thenext-lower product place. These carries are referenced with asterisks inFIG. 4.

As derives from FIG. 4, a circuit arranged tree-like arises for therealization of the value of a product place, this circuit beingrespectively based on AND circuits UD and becoming narrower and narrowerwith the assistance of adder circuits AD until only one adder circuit ofthe highest stage required is still present.

The number of adder stages is dependent on the size of the multiplierfactor and is also dependent on whether the multiplication of twopositive numbers or of two numbers in two's complement is to be carriedout. For a multiplier that multiplies only positive numbers, the numberof adder stages is established by the binary logarithm log₂ n (n is thenumber of bits of the multiplier factor) rounded up to the next, wholenumber and then de-incremented by 1). For a multiplier for two'scomplement numbers, the number of adder stages corresponds to log, (n+1)rounded up to the next, whole number and de-incremented by 1.

The arrangement of the individual cells that each respectively contain acircuit according to FIG. 4 on a semiconductor module is schematicallyshown in FIG. 5 for that case that numbers free of operational signs aremultiplied with one another. Individual cells SL lie side-by-side andform a multiplier field MF. The partial products are formed in the cellsSL and added up per product place. The result appears as sum bit S andcarry bit C at the output of every cell SL. The sum bit at the output ofthe cell SL must still be operated with the carry of the precedingproduct place. This ensues in the adder circuit ADD to which the value Sof the individual cells and a carry C of a preceding cell is supplied.The correct value P of the corresponding product place then appears atthe output of the adder circuit ADD. This value P is written into anoutput register AG. The multiplicand A is written into the inputregister RE1 and is supplied to the cells SL from there. As shown inFIG. 3, the most significant bit Am attached to the multiplicand issupplied to the cells that generate the partial products of the FieldII. Since these are always 0 in the case of FIG. 5, the most significantbit must be set to 0. The multiplier factor B is supplied to an inputregister RE 2 and proceeds to the individual cells SL of the multipliervia an additional circuit TE that serves the purpose of testing. Theregister RE2 also contains places for a test signal TN1 and for aninitial carry CIN.

FIG. 6 shows the fundamental structure of a multiplier that multipliesbinary numbers represented in two's complement. It differs from themultiplier of FIG. 5 in that, first, the most significant bit of themultiplicand A that represents the operational sign is supplied to thecells SL that must generate the partial products in the Field II. Afurther difference is comprised therein that the register RE2 for themultiplier factor provides a place for a second test signal TM2. Theexecution of the register RE1 may be taken from FIG. 16, the executionof the register RE2 may be taken from FIG. 18 and the execution of thetest circuit TE may be taken from FIGS. 17 and 19.

The more detailed arrangement of the AND circuits and adder circuitsthat are shown in FIG. 4 in the cell SL derives from FIG. 7. Theindividual cells SL of the multiplier field MF are arranged in the chipin the fashion to be derived from FIG. 7. Let the cell SL0 thatgenerates the least significant product place of FIG. 3 be explained asan example. From top to bottom, an AND circuit UD1 is first arranged inthe first row Z1, followed by an adder circuit of the first stage ADI1.The AND circuit UD1 is supplied with four lines for four bits B₀ throughB₃ of the multiplier factor and with one bit A₀ of the multiplicand. AsFIG. 3 shows, the partial product A₀ B₀ required for generating theproduct place P₀ can thus be generated. The other lines indicated at theAND circuit UD1 in the cell SL0 serve the purpose of checking themultiplier field and generate the Field I. The adder circuit ADI1 of thefirst stage that follows the AND circuit UD1 operates the partialproducts of the AND circuit UD1. The lines indicated at the edge arerequired for testing the multiplier field MF. They derive from FIG. 19.

The adder circuit ADII is followed by an AND circuit UD1 of the secondrow Z2 that carries out the operation of the multiplicand bits with themultiplier factor bits B₄ through B₆. In terms of structure, itcorresponds to the AND circuit UD1 of the first row Z1. The AND circuitUD1 of the second row Z2 is followed by an adder circuit ADI2 of thefirst stage that operates the partial products of the AND circuit UD1.The adder circuit ADI2 is followed by an adder circuit of the secondstage that is referenced ADII1. The output signals of the two addercircuits of the first stage, namely ADI1 and ADI2, are summed up withthis adder circuit of the second stage.

A wiring channel wherein the lines on which the multiplicand bits aretransmitted respectively offset by one row can be provided between therows Z1 and Z2. The offset corresponds to the matrix, for example FIG.3.

The row Z2 can be followed by further rows that are correspondinglyconstructed. They are always composed of a series of AND circuits UD1that is followed by at least one adder circuit of the first adder stageAD1.

The structure of the AND circuits UD1 can be derived from FIG. 8. TheAND circuit is composed of four AND elements UG1 through UG4 that arerealized here as NAND elements having connected inverter. Via theterminal EA0, the first AND element UG1 is supplied with the mostsignificant multiplicand bit of the four multiplicand bits to beoperated here and, via the input EB0, is supplied with the leastsignificant multiplier factor bit of the multiplier factor bits to beoperated. The second most significant multiplicand bit is supplied tothe second AND element UG2 via the input EA1 and the second leastsignificant multiplier factor bit is supplied thereto via the input EB1,etc., until the AND element UG4 is supplied with the least significantmultiplicand bit at the input EA3 and with the most significantmultiplier factor bit at the input EB3. It may also be seen from FIG. 8how the lines for the multiplicand bit are conducted offset to theneighboring cell, whereas the lines for the multiplier factor bits areconducted horizontally through the AND circuit.

For the last four multiplier factor bits to be operated, i.e. the mostsignificant multiplier bits or, according to FIG. 3, the multiplier bitsof the last four rows of the matrix, a row Z₁ is provided according toFIG. 7 that contains AND circuits in the first array and adder circuitsof various stages in the following rows. Corresponding to theabove-recited equation, the number of adder stages depends on the widthof the multiplier factor to be operated.

The execution of the AND circuits in the array of the row Z₁ isdifferent and depends on what partial products are to be formed. Acomparison to FIG. 3 shows that somewhat different AND circuits forforming the partial product are needed in the last four rows of thematrix that cover the multiplier factor bits B₄ through B₇.Correspondingly, there are different AND circuits. AND circuits UD2 areemployed from cell SL0 up to and including cell 4k-3, wherebyk=(ndiv4)+1 applies (div is the integer division without remainder).With reference to the matrix of FIG. 3, n=4 applies and a value of 2thus derives for k. What this means is that an AND circuit UD2 isemployed up to cell 5. This can also be easily accomplished according toFIG. 3. The structure of this AND circuit UD2 derives from FIG. 9. Itmay be seen that this AND circuit UD2 hardly differs from the ANDcircuit UD1. The significant difference may be seen therein that a linefor a test signal ET2 passes through the AND circuit UD2. The job of thetest signal ET2 shall be explained later.

The next AND circuit in the array, namely the AND circuit UD3 thataffects the sixth cell in the example of FIG. 3 is likewise nearlyidentical to the AND circuit UD2; it differs only in that the line forthe test signal ET2 splits into two lines, namely a line for forwardingthe test signal ET2 in inverted form ENT2 and in non-inverted form ET2.

A modification of the AND circuit derives with the AND circuit UD4 thataffects the cell 4k-1, i.e. the seventh cell SL7 of FIG. 3. It may beseen from FIG. 3 that this AND circuit--by comparison to the other ANDcircuits--must operate a multiplicand bit inverted with the multiplierfactor bit in an AND element and must also additionally through-connectthe most significant bit B3 of the multiplier factor to the output ofthe AND circuit in an AND element. An execution of this AND circuit UD4derives from FIG. 11. Whereas two AND elements UG5 and UG6 have notexperienced any modification, the AND elements UG7 and UG8 are somewhatdifferently constructed. The AND element UG7 is likewise composed of anNAND element and of an invertor but an EXNOR circuit that is driven viathe test signals ET2 and ENT2 is connected to the input EA2. In theoperating case, this EXNOR circuit is wired such that it connects themultiplicand bit at the input EA2 inverted to the input of the NANDelement of the AND element UG7. In the test case, by contrast, the EXNORcircuit is driven such via the test signals ET2 and ENT2 that themultiplicand bit at the input EA2 is through-connected to the ANDelement not inverted. What this means is that the AND element UG7 istreated like all other AND elements in the test case and, thus, thetesting is simplified. The AND element UG8 is composed of an inverterand of a multiplexer circuit MUXN arranged at the output. Themultiplexer circuit MUXN is likewise driven by the test signals ET2 andENT2. It is wired such in the operating case that the multiplier factorbit at the input EB2 is through-connected to the output, this is themost significant bit B3 in FIG. 3. In the test case, by contrast, thebit adjacent at the inputs EA3 and EB3 is through-connected via the NANDelement, so that the AND element UG8 works like the other AND elementsof the AND circuits in the test case.

The remaining AND circuits of the row Z1 RAND circuits UD5 that areconstructed according to the AND circuit UD4--except for the AND elementUG8 that is not required since the most significant bit of themultiplier factor need not be through-connected to the output here. Anembodiment derives from FIG. 12. It may be seen that, agreeing with thematrix in FIG. 3, the inverted multiplicand bits to be operated with themost significant bit B3 of the multiplier factor are operated in the ANDelement UG7 and that the remaining AND elements have normal structure.The test signals ET2 and ENT2 are again provided for switching the ANDelement UG7 from the operating case into the test case.

An embodiment of the EXNOR circuit derives from FIG. 14; an embodimentof the multiplexer circuit MUXN derives from FIG. 13.

An adder circuit derives from FIG. 15. It may be seen that the addercircuit is composed of two full adders, namely of the full adder VA1 andof the full adder VA2. The full adder VA1 has three inputs E1, E2, E3and two outputs, one output for the sum bit SB and one output for thecarry bit CBN that is output inverted in this case. The full adder VA2likewise has three inputs E4, E5, E6. The input E5 is supplied with thesum bit SB of the first full adder VA1; the input E6 is supplied with aninverted carry bit from a neighboring cell. The input E4 can be suppliedwith either a partial product or with a carry bit dependent on the stageto which the adder circuit belongs. The full adder VA2 outputs the sumbit SB at the output A3 and the carry bit CB at the output A4.

When the adder circuit of FIG. 15 is used in the first stage, i.e. asadder circuit AD1, then a respective partial product is supplied at theinput E1, E2, E3, a partial product is likewise supplied to the inputE4, the sum bit is supplied to the input E5 and a carry bit is suppliedto the input E6 from the first full adder of the adder circuit of thefirst stage of the next, less-significant cell. This can be derived fromFIG. 19. Two least significant cells SL1 and SL0 are shown here. In thecell SL1, the adder circuit AD1 of the first stage--that is connected toan allocated AND circuit--has partial products supplied to it at theinputs E1 through E3, likewise has a partial product supplied to it atthe input E4, has the sum bit of the first full adder supplied to it atthe input E5 and has a carry bit of the first full adder of the addercircuit of the first stage arranged neighboring it supplied to it at theinput E6.

The adder circuit ADII1 of the second stage of the cell SL1 is suppliedwith the sum bit of the adder circuit ADI2 at the input E1, with thecarry bit of the adder circuit ADI2 of the cell SL0 at the input E2,with the carry bit of the adder circuit ADI1 of the cell SL0 at theinput E3. The sum bit of the adder circuit ADI1 of the same cell SL1 isadjacent at the input E4; the sum bit of the allocated full adder VA1 isadjacent at the input E5; and the carry bit of the adder circuit ADII1of the cell SL0, namely of the first full adder VA1 thereof, is adjacentat the input E6.

The adder circuits of the higher stages are then connected according toa corresponding rule. In an adder circuit of a higher stage, a sum bitand two carry bits are always operated in the first full adder and twosum bits and one carry bit are always operated in the second full adder.

A higher stage of adder circuits thus always operates the sum bit andcarry bit of adder circuits of a lower stage. It can thereby derive thatan adder circuit of a higher stage must operate the output signals ofadder circuits of different stages. This is the case when the pluralityof adder circuits per stage is not divisible by two.

It has already been stated that five different AND circuits that,however, differ only slightly are required given the two's complementrepresentation of the binary numbers to be operated. The reason for thishas been set forth in conjunction with FIG. 3. Only one AND circuit UD1is required when only positive numbers without operational sign bit areto be operated with one another.

In order to be able to test the multiplier, namely the multiplier fieldMF, prescribed bit patterns must be supplied to the AND circuits UD andto the adder circuits AD and the output signals output by the cells atthe outputs of every cell SL must be compared to rated signals. Thecomparison then shows whether a cell works faultlessly or not. Thetesting of the cells requires comparatively simple bit patterns at theinput when the cells SL can all be operated in the same way. In order toachieve this, a test circuit TE and test signals TM are respectivelyprovided in FIGS. 5 and 6. The structure of the test circuit TE and thefunction of the test signals TM1 in FIG. 5 or, respectively, TM1 and TM2in FIG. 6 shall now be set forth in conjunction with the circuits ofFIGS. 15 through 18 and the above-explained AND circuits.

According to FIG. 6, the multiplicand bit A is supplied such to the ANDcircuits in the Field III that a respective multiplicand bit is suppliedto one cell and this multiplicand bit is then forwarded offset to theneighboring cell. The multiplicand bits in the Field II all correspondto the most significant bit of the multiplicand and are thus supplied toevery cell that is more significant than the most significant bit of themultiplicand. FIG. 16 shows a circuit via which this can be carried out.The multiplicand bits A₀ through A_(n-1) are respectively supplied to acell ZL₀ through ZL_(m-1). The most significant multiplicand bit A_(m-1)is then supplied to the remaining cells, namely to the cells Z1L_(m)-ZL_(m+-1).

The AND circuits in the Field I that receive a 0 at their inputs for themultiplicand in the operating case must be driven with a specificmultiplicand bit in the test case. This is the multiplicand bit A₀ inthe exemplary embodiment. A circuit according to FIG. 17 is provided inorder to achieve this. The multiplicand bit A₀ is conducted via an ANDelement UGT1 to the AND elements UG of the AND circuits that generatethe partial products in the Field I. The test signal TM1 is alsoadjacent at the AND element UGT1. Dependent on what value the testsignal TM1 has, the output signal of the AND element UGT1 is 0 or A₀.The expansion of the multiplier factor according to FIG. 3 leads theretothat 1=4k-1 AND elements must driven. In the exemplary embodiment ofFIG. 3, 1 would be equal to 7.

Since A₀ is supplied to the AND elements in the Field I in the test caseand since the multiplier bits are independently adjustable, the ANDelements can be tested with various values.

The explanation of FIG. 7 has shown that AND elements UD2 through UD5are used in the row Z1. The operating case has thereby been explainedthere. In the operating case, the most significant bits of themultiplier factor, for example the multiplier factor bit B₃ in FIG. 3,are supplied to the AND elements in the operating case, except to oneAND element. FIG. 18 shows a circuit with which this is achieved. Themultiplier factor bits Bn-1 through B_(4k-2) are through-connected tothe AND elements via multiplexer MUX dependent on the test signal TM1.In the test case, by contrast, these AND elements must be capable ofbeing individually set with their multiplier factor inputs. The testsignal TM1 is again utilized for this purpose, this switching themultiplexer MUX such that the expanded multiplier factor bits Bn throughB_(4k-1) are connected to the AND elements. The expanded multiplierfactor bit B_(4k-1) is conducted via an AND element UGT2 that is drivenby the test signal TM1 to an AND element, namely to the AND element forthe row within the matrix in which the most significant bit of themultiplier factor is added to the partial products of a column, i.e. tothe last row of the matrix in FIG. 3. Dependent on the value of the testsignal TM1, a 0 or the multiplier factor bit B_(4k-1) appears at theoutput of the AND element UGT2. In the operating case, a 0 is output atthe output of the AND element UGT2; in the test case, the multiplierfactor bit B_(4k-1) is output thereat. It is thus possible toindividually test the allocated AND elements.

It must also be seen to in the test case that the carry inputs of theadder circuits of the cell SL0 are supplied with the same carry as thecell SL1. The carry inputs of the adder circuits of the remaining cellsare connected in the usual way. In order to achieve this, the carryoutput of the first full adder of the adder circuit of the first stageADII according to FIG. 19 is conducted via an AND element UGT3 to thecarry input of the second full adder of the same adder circuit. Thecarry output of the adder circuit ADII of the first stage is thenconnected via a further AND element UGT4 to the carry input of the nextadder circuit ADII1 of the second stage. The analogous case also appliesto the other adder circuits. For example, the adder circuit ADI2 of thesecond row has its carry output connected to the carry input of theadder circuit ADII1 of the second stage, etc. The interconnection can bederived from FIG. 19. With the assistance of the test signal TM1 that isconnected to the AND elements UGT3 and UGT4, either the carry signalfrom a full adder of this or of a preceding stage or the value 0 can beapplied to the carry inputs. It is thus achieved that the carry signalthat is evaluated in the first cell SL0 is 0 in the operating case but adefined carry proceeds to the adder circuits of the first cell SL0 inthe test mode. It is thus possible that the application of test signalsmakes it possible to generate defined output signals that can be checkedfor their correctness. The outlay required for this purpose is low.

The invention is not limited to the particular details of the apparatusdepicted and other modifications and applications are contemplated.Certain other changes may be made in the above described apparatuswithout departing from the true spirit and scope of the invention hereininvolved. It is intended, therefore, that the subject matter in theabove depiction shall be interpreted as illustrative and not in alimiting sense.

We claim:
 1. A multiplier for performing an operation on an m-digitmultiplicand and an n-digit multiplier factor that are both representedas binary numbers, comprising:m+n cells arranged side-by-side,respectively one per product place, whereof each cell respectivelycontains AND circuits for forming partial products allocated to theproduct digit and adder circuits for summing up the partial products forthis product digit; each cell of the m+n cells having, a first stagehaving a respective adder circuit for each AND circuit, each addercircuit operating on a partial product formed by a respective ANDcircuit to form a partial sum and a partial carry; a second stage havinga plurality of adder circuits, each adder circuit of the second stageoperating on at least two partial sums formed by respective addercircuits of the first stage and at least two partial carries of anext-less significant product digit of the first stage to form a furtherpartial sum and a further partial carry; a third stage having aplurality of adder circuits, each adder circuit of the third stageoperating on at least two partial sums formed by respective addercircuits of the second stage and at least two partial carries of anext-less significant product digit of a second stage to form anotherfurther partial sum and another further partial carry; an ith stagehaving a plurality of adder circuits, each adder circuit of the ithstage operating on at least two partial sums formed by respective addercircuits of a (i-1)th stage and at least two partial carries of anext-less significant product digit of a (i-1)th stage to form anadditional further partial sum and an additional further partial carry;a final adder circuit that operates on the final sum formed byrespective adder circuits of the ith stage and two partial carries of anext-less significant product digit of an ith stage to form a final sumand a final carry; and a further added circuit that operates on thefinal sum formed by the final adder circuit and a final carry of anext-less significant product digit to form a value for the productdigit of the respective cell; for each cell of the m+n cells, a firstsequence defined by, a first AND circuit of the first stage beingfollowed by a first adder circuit of the first stage, the first addercircuit of the first stage being followed by a second AND circuit of thefirst stage, the second AND circuit of the first stage being followed bya second adder circuit of the first stage, the second AND circuit of thefirst stage being followed by a first adder circuit of the second stagethat receives signals from the first and second adder circuits of thefirst stage, a second sequence defined by, a series of first sequencesthat ends with a last adder circuit of the second stage, the last addercircuit of the second stage being followed by a first adder circuit ofthe third stage that receives signals from the adder circuits of thesecond stage, and a jth sequence defined by a series of j-1 sequences, alast element in the jth sequence being said final adder circuit.
 2. Themultiplier according to claim 1, wherein each adder circuit is composedof first and second full adders connected in series, each of which hasrespectively three inputs.
 3. The multiplier according to claim 2,wherein every AND circuit is composed of four AND elements whereof eachoperates on one bit of the multiplicand and one bit of the multiplierfactor.
 4. The multiplier according to claim 3, wherein an adder circuitis connected in the following way:three partial products are received atfirst, second and third inputs of the first full adder; a fourth partialproduct is received at a first input of the second full adder, a sum bitof the first full adder is received at a second input of the second fulladder, a carry bit from the first full adder of the adder circuit of thefirst stage allocated to the next-less significant product digit isreceived at a third input of the second full adder.
 5. The multiplieraccording to claim 4, wherein an adder circuit of a more significantstage is connected in the following way:a sum bit from an adder circuitof a less significant stage is received at a first input of the firstfull adder, a respective carry bit from carry outputs of adder circuitsof a lower stage allocated to a next-less significant product digit isreceived at second and third inputs of the first full adder; a sum bitof an adder circuit of a less-significant stage is received at a firstinput of the second full adder, a sum bit from the first full adder ofthe same stage is received at a second input of the second full adderand a carry bit from a first full adder of an adder circuit of the samestage allocated to a next-less significant product digit place isreceived at a third input of the second full adder.
 6. The multiplieraccording to claim 1, wherein all cells comprise an identical pluralityof AND circuits and an identical plurality of adder circuits; wherein amultiplicand input of AND circuits that generate partial products, in aField I, that are nit required for generating a value of lesssignificant product digits is set to 0; and wherein a multiplicand inputof AND circuits that generate partial products, in a Field II, that arenot required for generating the value of more significant product digitsis set to 0 given multiplication of numbers without an operational sign.7. The multiplier according to claim 1, wherein all cells comprise anidentical plurality of AND circuits and an identical plurality of addercircuits; wherein, for multiplication of binary numbers in two'scomplement representation, a multiplicand input of AND circuits thatgenerate partial products, in a Field I, not required for generating avalue of less significant product digits is set to 0; wherein amultiplicand input of AND circuits that generate partial products, in aField II, that are not required for generating a value of moresignificant product digits is connected to a most significant bit of themultiplicand; wherein bits of the multiplicand to be operated on with anoperational sign bit of the multiplier factor are applied to theallocated AND circuits; and wherein a most significant bit of themultiplier factor is added at the product digit where at a mostsignificant bit of the multiplier factor is operated on with a leastsignificant bit of the multiplicand.
 8. The multiplier according toclaim 7, wherein for a test case given a multiplication of binarynumbers of two's complement representation, a plurality of bits isdoubled; wherein the partial products, in the Field II, arising as aresult thereof are formed of a most significant bit of the multiplicandand of bits of the multiplier factor; wherein a plurality of multiplierfactor bits of the multiplier factor is always expanded to a numberdivisible by four, whereby a most significant bit of the expansion is 0in an operating case and is variable in the test case, less significantbits of expansion in the operating case equal to a most significant bitof the multiplier factor being individually adjustable in the test case.9. The multiplier according to claim 8, wherein AND elements of ANDcircuits that generate partial products in the Field I are connected toa least a significant bit of the multiplicand in the test case.
 10. Themultiplier according to claim 9, wherein AND elements of AND circuitsthat form partial products with inverted multiplicands are supplied withmultiplicands non-inverted in the test case.
 11. The multiplieraccording to claim 8, wherein an AND circuit having the following ANDelements is contained in a last row of AND circuits;one AND element viawhich an allocated bit of the multiplicand is supplied inverted in theoperating case but to which this bit of the multiplicand is suppliednon-inverted in the test case; one AND element to which the mostsignificant bit of the multiplier factor expansion is conducted and atwhose output a multiplexer is arranged that through-connects either anoutput signal of the AND element in the test case or, in the operatingcase, the most significant bit of the multiplier factor; further ANDelements that form either partial products of the allocated bits of themultiplicand or bits of the multiplier factor or the expansion thereof.12. The multiplier according to claim 8, wherein in the test case, carryinputs of the adder circuits allocated to a least significant productdigit are connected to one another in the following way:a carry input ofthe second full adder of an adder circuit of the first stage isconnected to a carry output of the first full adder of this stage; carryinputs of the first full adder of the second stage are connected tocarry outputs of the second full adder of the adder circuits of thefirst stage, and carry inputs of the first full adder of an ith stageare connected to carry outputs of the second full adder of an (i-1)thstage, so that the carriers successively run through the individualadder circuits of successive stages.